`timescale 1 ps/ 1 ps;

module test (clk, reset, out);
input clk, reset;
output [4:0] out;
reg [4:0] count;

always @ (posedge clk)
begin
if (reset)
 count <= 0;
 else if (count == 5'b11111)
  count <= 5'b00000;
  else
  count <= count +5'b1;
end
assign out = count;
endmodule