`timescale 1 ps/ 1 ps;
module test_tb();
// constants                                           
// test vector input registers
reg clk;
reg reset;
// wires                                               
wire [4:0] out;

// assign statements (if any)                          
test i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.out(out),
	.reset(reset)
);
initial                                                
begin                                                  
clk=0;     
reset = 1;
#20 reset = 0;                                    
$display("Running testbench");                       
end  
                                                  
always                                                 
                  
begin                                                  
#5 clk = 1; 
#5 clk = 0; 
$monitor ("Reset is = %b and Clock is = %b and Output is = %b \n", reset, clk, out);
                              
end    
                                                
endmodule