Welcome to Digital VLSI Architecture Course Website (Fall 2011): (31-01-2012)
The marks for the HWs, Midterm and Final are posted here. It is not complete and the project marks will be added soon. You can come to see your final papers next Saturday at 11:00.
I. Instructor: Mahdi Shabany
Comprehensive understanding of the digital design flow, including the algorithmic level issues, architecture optimization, hardware description languages, as well as the digital Application Specific Integrated Circuit (ASIC) design concerns in the transistor/system level is extremely important for today’s digital designers. This course is designed to address most of these issues through lectures, projects and lab assignments. The course will give insight on how to get from a signal processing algorithm to an efficient VLSI implementation using various architectural techniques while considering a given set of criteria. In fact, the course provides a practical understanding of the implementation strategies for digital ICs, existing VLSI technologies, fundamentals of digital ASIC design, RTL coding for synthesis, common digital signal processing algorithms, efficient techniques for floating‐point and fixed‐point simulations, as well as VLSI techniques for high‐speed/low‐power designs. The main part of the course will be focused on the design of application specific architectures that can be implemented on either reconfigurable hardware, e.g. Field Programmable Gate Arrays (FPGAs), or ASIC. State‐of‐the‐art design tools will be used to support the course work. As a part of the course requirement is a term project on the design and ASIC implementation (full chip) of a digital sub‐system, which is assigned at the beginning of the semester and will be completed in parallel to the lectures.
III. Lecture Notes:
§ Course Description (19-09-2011)
§ DVB Standard (19-09-2011)
§ Pipelining and Parallel Processing (08-10-2011)
§ Fixed-point (27-12-2011)
§ Assignment #1 (05-10-2011)
§ Assignment #2 (11-10-2011)
§ Assignment#3 (20-11-2011)
§ Assignment #4 (29-11-2011)
§ Assignment #5 (Add the outer interleaver to your design both in the transmitter and the receiver) (29-11-2011)
§ Assignment #6: (From the Parhi Book) (27-12-2011)
1. Problem 12, 16 Chapter 7
2. Problem 4 of Chapter 10
3. Problem 14 of Chapter 15
V. Modelsim: (19-09-2011)
§ Please note that you need to install Modelsim on your machine. It is recommended to do the following tutorial.
Ø There are two files used in this tutorial, which you can download from here, test.v, test_tb.v. Please copy them in the work directory you want to run the Modelsim tutorial. Please note that these files are used instead of the files suggested by the Modelsim tutorial in page T-19 of the tutorial.
VI. Textbook: (19-09-2011)
§ VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi
§ DSP Integrated Circuits, Lars Wanhammar, 1998.
VII. References: (19-09-2011)
§ Introduction to Logic Synthesis using Verilog HDL, Robert Reese, Mitchell Thornton, 2006.
§ Fundamentals of Digital Logic with Verilog Design, 2nd Edition, [Appendix A: Verilog], S. Brown, 2006.
§ Verilog Coding for Logic Synthesis, Weng Fook Lee , 2003.
§ Verilog HDL Synthesis, A Practical Primer by J. Bhasker, 1998
§ ASIC World Verilog (Useful tutorials/examples)
§ Paper 1
§ Paper 2
§ Paper 3
§ Paper 4
§ Paper 5