بسم الله الرحمن الرحیم

A number of chips that I or my students designed in various CMOS technologies.

CMOS, 0.18um, TSMC

Nov. 2004

The basic idea of the segmented virtual grounding scheme is implemented in this work.

CMOS, 0.13um, IBM , Aug. 2005

A design for verification of the theory of dynamic data stability in SRAM units.

CMOS, 0.13um, IBM , Feb. 2005

Dynamic Data Stability in SRAM Cells

Low-energy and low-leakage 40Kb SRAM

Freq. Digitizer for Bluetooth receivers

Silicon Valley

The idea of current sensing combined with an interesting form of offset cancellation.

CMOS, 0.18um, TSMC, May 06

The idea of on chip testing of analog units using on chip ring oscillators and DC levels at IOs.

CMOS, 0.18um, TSMC, May 06

Built-in Self test for Analog Circuits

Offset cancelled current Sense Amp. (OCCSA) for SRAMs

64Kb 64Kb Symmetric 4T SRAM+16Kb Asym. 4T SRAM Blck

CMOS, 90nm, STMicro, July, 07

4T SRAM cells (Asym. and Sym.)

Made for VoIP applications

CMOS 0.35u, 2001

A Quad Channel Voice Codec

The idea of having symmetric (AES), asymmetric (RSA, ECC) as well as Hash algorithms on a single VLIW processor. Designed by me and Mr. Haghi and tested by my student Mr. Bahadori. (08-07)

CMOS, 0.18um, TSMC, May 06

Multi-standard multi-mode Crypto-processor

The idea of cancelling the offset of a current SA before the operation and using a voltage SA to get full swing. Done by Mrs. Attarzadeh. 2009

Hybrid Current/Voltage Sense Amp. for high-speed SRAMS with Offset cancellation

The DVB-T tuner as a part of DVB receiver program in the contract with IRIB. The design won the national award of Khwarizmi. It was designed under my Analog/RF team: Dr. Saeedi, Mr. Chardori and Mr. Behmanesh. June 2010.

DVB-T Tuner

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. Done by Mr. Chardori. 2010

A Sub 1 Volt High PSRR CMOS Bandgap voltage

reference

Designed and tested by Dr. Chardori, the IC involves new ideas on the design of a very high speed Flash ADC. It incorporates new ways of offset cancellation and certain techniques to reduce kickback noise. It was designed and tested in 2012.

A 4 bit 1.6 GS/Sec Flash ADC

Designed and tested by Mr. Eslampanah, a 3-digit Quaternary to Analog Converter (QAC) and a 4-digit Ternary to Analog Converter (TAC). The quaternary DAC occupies less area rather than the equal binary DAC.

Structure of Switch Capacitor Digital to Analog Converter

A low-power ASK demodulator for RFID and biomedical applications. The design was based on a voltage to current comparator. It was designed and tested by Mrs. Narges Mousavi with the cooperation of Dr. Jalali from Shahed University.

An ASK demodulator

Designed and tested by Mr. Khorami, a new switching of stepwise adiabatic circuits was proposed and tested that speeds up the charging process by two times. Also, a nanometer current source was tested which breaks a deadlock in peaking current sources.

Stepwise tank, asynchroun control circuit, nano-amp current reference, and some low-power circuits.